During front end-of-the-line processing, a plurality of semiconductor devices (e.g., transistors, resistors, capacitors, and the like) are formed on a semiconductor wafer. During back end-of-the-line (BEOL) processing, the semiconductor devices are interconnected to form a plurality of integrated circuits on the wafer, which are subsequently separated into individual die during wafer dicing. Interconnection of the semiconductor devices is accomplished via the formation of a plurality of BEOL layers, which include, in part, a number of metallization layers and a number of intermetal dielectric layers. The BEOL layers are divided into a number of successive metal levels, with each metal level commonly formed utilizing a damascene or a dual damascene technique. For example, during a generalized damascene process utilized to form the M1 metal level, an intermetal dielectric material (IMD) is first deposited over a previously deposited pre-metal dielectric layer; the IMD is etched to create a pattern therein; the pattern is filled with a conductive metal, such as copper; the excess copper is removed utilizing a chemical mechanical planarization (CMP) process to yield a number of metal interconnect lines within the IMD; and then an additional IMD (commonly referred as a “capping layer”) is deposited over the patterned interconnect lines and previously-deposited IMD. Additional metal levels (e.g., the M2 metal level, the M3 metal level, etc.) are successively formed in a similar manner, with many conventional integrated circuits including up to twelve metal levels in total.
For process development reasons, it is often desirable to monitor characteristics pertaining to the layers formed during back-end-of-the-line (BEOL) processing. In current practice, at least two metrological methods are commonly employed to monitor BEOL layer thickness. Each metrological method is typically performed after chemical mechanical planarization and prior to formation of the capping layer. In the first commonly-employed method, an interferometer directs a beam of light through the IMD and against a relatively large (e.g., >50 microns), non-patterned metal pad (the “measurement pad”) provided beneath the uppermost metal level. The light beam is reflected from the measurement pad, propagates back through the IMD, and is ultimately received by an optical receiver. The phase change between the ingoing and outgoing light waves is measured and utilized to estimate the thickness of the IMD overlying the measurement pad. By comparison, in the second commonly-employed metrological method, a scatterometer directs a beam of electromagnetic (e.g., microwave) energy against a lattice-like metal structure (commonly referred to as a “grating structure”) formed within the IMD of the newly-formed metal level. When striking the grating structure, the beam scatters in relation to the depth of the grating structure. The degree to which the beam scatters is then measured and utilized to estimate the depth of the grating structure and, therefore, the depth of the metal interconnect lines within the measured metal level.
Each of the above-described metrological methods is limited in certain respects. For example, both the interferometer- and the scatterometer-based methods have limitations associated with reliability and accuracy. In addition, the performance of either of above-described metrological methods requires an independent metrological step and separate tool set; as a result, both metrological methods prolong the semiconductor fabrication process and incur undesirable CMP-to-capping time delay during which oxidation of the metal interconnect lines can occur. As a further disadvantage, the above-described metrological methods are generally incapable of measuring other potentially useful characteristics pertaining to the BEOL layers; in particular, both methods are generally incapable of measuring the dielectric constant at various locations across the BEOL layers, and the scatterometer-based method is further unable to measure IMD thickness. The interferometer-based method described above is also limited in several unique manners. For example, the CMP removal rate of the IMD overlying the measurement pad often differs from the removal of the IMD overlying the metal interconnect lines formed in the underlying metal level. Thus, the thickness of the IMD over the measurement pad is often not representative of the average IMD thickness over the measured metal level. Furthermore, to ensure sufficient reliability of interferometer-based measurements, the measurement pad may be required to have a minimum thickness that excludes usage in conjunction with 22 nanometer (nm) semiconductor nodes and below. As a still further disadvantage, the recent usage of ultra low-k IMD materials has enabled the thickness of metal interconnect lines to be decreased to dimensions that are difficult to accurately monitor utilizing interferometer-based methods. Finally, the optical characteristics (e.g., reflectivity index) of the ultra low-k IMD materials can also change due to chemical reaction with the slurry applied during CMP processing and thus introduce still further inaccuracies in interferometer-based measurements.
Considering the above, it is desirable to provide embodiments of a monitoring method suitable for monitoring one or more characteristics pertaining to layers formed during the back end-of-the-line processing of a semiconductor wafer, such as BEOL layer thickness, via over-etch depth, and/or dielectric constant variation across the wafer. Preferably, embodiments of such a monitoring method could be reliably performed utilizing existing in-line electrical test equipment thereby eliminating the need for a separate tool set and minimizing CMP-to-capping time delay. It would also be desirable for embodiments of such a monitoring method to be compatible with ultra low-k IMD materials and semiconductor nodes equal to or less than 22 nm. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended Claims, taken in conjunction with the accompanying Drawings and the foregoing Technical Field and Background.